Assertion-based Verification Of Amber25Processor Core

Throughout the last decades, as technology advances, microprocessors havecome to be a vital and inseparable part of the modern electronic designs world, becomingthe digital brain of numerous electronic devices and gadgets that make today’s lifestylepossible. Processors are capable of performing computation at astonishingly high speedsand are extremely integrated, occupying only a few square centimeters of silicon die.However this computational power comes at a price; the task of verifying a modernmicroprocessor and guaranteeing correctness of its operation is increasingly challengingfrom the academic level to the industry level. In critical application domains, such ascommunication, medicine, transportation, finances, military, the requirement for thecomputers to always behave correctly becomes critical as well.Attempting to deliver higherperformance to end-user, additional millions of transistors are fit on each new processorgeneration which makes more complex designs possible, on the other side this increase inthe design complexity brings to the increasing challenge in term of effective verification ofthe processor designs.In the initial stage of most design cycles, the extensive efforts are exclusively investedon how to improve the design traditional metrics like performance, power and area. Thedesign for verification is not explicitly considered at this earlier stage where the mostinfluential decisions are made. The fact that verification is often considered after the designhas been completed makes the resulting design become more difficult to be verified;therefore processor manufacturers are forced to employ immense verification teams toeliminate critical design bugs in a timely manner. Currently, ensuring that processor designsare correct represent a major challenge for the computing industry consuming the majority(up to70%) of the resources allocated for the creation of a new processor. The main reasonof this challenge in the design verification process is compounded in the current usedprocessor design flow.In this thesis, in order to reduce the time spent on the design verification we propose toconsider the verifiability as a critical design constraint at the initial stage of the design cycle,we have showed the importance of having a verification specification written as soon as thearchitectural specification document is complete. We provided the way to effectively applythe assertions based verification methodology in the design cycle life; we highlighted theadvantages of writing the verification plan serving as the roadmap for the verification team.We also explained how difficult it is to add assertions so late in the design cycle, addingassertions at the last minute takes much longer which is a challenge for the time to marketof the final design and therefore more costly than it would have been to plan for assertionsearly at the initial stage of the design cycle.In this research we intended to use assertions based verification (ABV) mechanism toverify the AMBER-25processor core system. SystemVerilog assertions (SVA) were usedduring our extensive verification process and have proved that it is very effective not onlyin capturing the design bugs in the system but also in providing the verification coverage details.A model of assertions based verification methodology was developed.The benefitsof this model are to make much easier the functional verification and guarantee the designfunctional correctness without affecting its performance, power and area metrics.