0.8μm SOI/CMOS SPICE Device Model Parameter Extraction

This thesis is one part of a national R&D project, which is named SOI SPICE/CMOS model parameter extraction technology. The major task was to design device test structure & test condition, extraction strategy & verification method, supply full set of 0.8μm SOI CMOS SPICE model parameters, have self-owned intellectual asset of patent, support the construction of 0.8μm SOI CMOS process platform, and work for the designing & manufacturing of anti-radiatin IC.The paper studied the Partially Depleted (PD) SOI MOSFET and BSIMPD model parameters. The paper design H-gate body-contact NMOS/PMOS device test structure,test condition, extraction strategy, optimize the model parameter extraction procedure, verify circuit. The paper designed the layout of test device & verify circuit, and had the photo mask made, finished the wafer processing, use Prober & HP4155B to test parameter, use IC-CAP software to extract & simulate parameter., use the verfy circuit to investigate the efficiency of extracted model parameter.The paper managed to finish the task of 0.8μm CMOS/SOI MOSFET SPICE paramter extraction & verification, simulated inverters, a 51-stage ring oscillator, a 16-bit divider to assess the model performance. The 0.8um PD SOI MOSFET SPICE model parameter extraction is demonstrated, and the simulation efficiency is studied. The achievement proved the ability to extract SOI device SPICE parameter. The aim of the study was achieved.