Realization Of Digital Inverter Controller For UPS Based On FPGA

Programmable Logic Device (PLD) is developed into great capacity, high capability and low cost along with the fast progress of micro-electronic. As the deputation of PLD, FPGA (Field Programmable Gate Array) and CPLD (Complicated Programmable Logic Device) are wildly used by the electronic design engineer in the world. Nowadays, the inverter controller is often composed by analog-digital or full digital controller based on microprocessor (DSP/MCU).But the microprocessor in common use is designed for general purpose, it is sure to have certain limitations, while the characteristic that the function can be defined by the customers of FPGA accounts for these limitations. So, in the past few years, the research on realization technology of FPGA for inverter controller has got more and more solicitude, and has become the new research direction of inverter controller.Altera Company is one of the biggest PLD producers in the world, and its CPLD/ FPGA and developing software Quartus II are wildly used in many fields in the country. In this paper, I have used a mature model of single-phase voltage source PWM inverter to realize the inverter controller with FPGA. Based on the realization of inverter controller with FPGA and the development technology of FPGA of Altera Company, I have carried out preliminary research on systematic function partition, hardware algorithm, and whole systematic hardware design and so on.Firstly, I have discussed the principle of Pulse Width Modulation (PWM), and then quoted the continuous and discrete mathematical models of a single-phase voltage source PWM inverter, and design the inverter voltage and current dual-loop controller based on pole-assignment.And then, I have introduced Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL), which is the FPGA developing language. In succession, the FPGA developing software and its developing flow are introduced. Subsequently, I have described the new technology of FPGA nowadays, and the developing principle and methods of FPGA. According to the characteristic and demanding of the system, I have selected EP1C6 as the core Integrated Circuit of the system, and analyzed the structure and the feature of EP1C6.In chapter four, I have planned for the system, and carried out the systematic function partition. On this foundation, I have carried out the hardware control algorithm unit such as: Digital Phase Locked Loop (DPLL), digital sampling system, Direct Digital Frequency Synthesis (DDS) standard sine wave generator, voltage current dual-loop controller PI hardware algorithm unit, SPWM producing unit, and so on. Their hardware algorithm have been studied .We have completed the modular design.Finally, I have discussed SOPC Builder and DSP Builder primarily. These two tools are both the FPGA system design environment. With SOPC builder, I have designed the embedded system based on Nios II. In the Nios II system, I have realized Serial Communication Interface (SCI) communication, which guaranteed the computer management for UPS system. Also, I have realized the Inner Integrated Circuit (I2C) communication, which guaranteed the system running dependably and continuously. In the end, the brief recommendation of the DSP Builder design method is given, with this method, I have designed standard sine wave generator based on DDS.