Design Of Radar Imaging Signal Processor Based On Standard Buses

The data volume and computation task of real-time high resolution radar imaging is huge, so the signal processor must have powerful computing and communicating capability. Multi DSP and multi board are always used for parallel processing to satisfy the requirements of real-time processing. However, as the upgrading of processing capability of DSP and the increasing of processing units, the balance between computation and communication becomes a serious problem. This paper discusses how to organize multi processing units to improve the efficiency of parallel processing effectively and how to solve the problems of chip-to-chip, board-to-board high speed data communication. A kind of real-time processor for radar imaging which satisfies different kinds of imaging algorithms has been developed for airborne platforms. The processor adopts the technique of distributed parallel processing and the technique of integrating standard buses with user-defined buses. Simultaneity, the design of switch circuit based on IP packet makes the communication between processors more flexible and extensible. Two project examples are presented to analyze the processing flow of real-time imaging.The signal processor must have better adaptability, reliability and stability as the development of missileborne and spaceborne real-time imaging technology. According to this trend, this paper proposes the real-time processing solution that FPGA and DSP process together and FPGA replaces DSP in some particular conditions. This paper also analyzes the problems resulted from that processing architecture. Finally we propose that the PCI Express is a follow-on replacement to the existing PCI parallel bus architecture.