Research On Real-time Video SAR Imaging Processing Technology Based On FPGA

Video SAR has attracted more and more attention because of its high frame rate,high resolution and dynamic scene detection capability.Because of its higher carrier frequency and shorter synthetic aperture time,Terahertz video SAR is easier to achieve high frame rate,which has better continuous imaging characteristics and is more conducive to real-time tracking of moving targets.Therefore,it is the best choice in some real-time detection application scenarios.Under the background of the continuous improvement of the development level of THz front-end devices,it is of great significance to carry out the research of THz video SAR real-time imaging system.Combined with the current development status of FPGA devices and corresponding development tools,this thesis proposes a video SAR real-time imaging system design scheme based on FPGA platform.Based on FSA imaging algorithm,this scheme gives a detailed module-level design scheme,and analyzes some engineering problems in the implementation process.Finally,the hardware simulation software is used to conduct presimulation verification of the whole system,and the imaging quality of the system is evaluated through the simulation results,and the imaging time and imaging delay are analyzed.The results show that this design scheme can be used as a basic design structure of video SAR real-time imaging system,and can be further upgraded on this basis.The main contents of this thesis are as follows:Firstly,the FSA imaging algorithm is theoretically analyzed and its basic algorithm flow is introduced,which lays a foundation for the subsequent algorithm transplantation to FPGA platform.The parameter constraint relation of video SAR system is studied and analyzed,and a set of parameter scheme which can be realized in the terahertz band is given based on the current development level of terahertz devices.The frame rate and image points in video SAR real-time imaging system are analyzed.Then,the general calculation formula of read and write efficiency is analyzed in combination with DDR timing parameters.On this basis,the basic principle of linear mapping matrix transpose algorithm and read and write efficiency of piecewise storage are analyzed.Based on the analysis of data storage format,the constraint formula of data processing module channel parallelism is given,and then the top-level scheme design of the system is given.Under the framework of the top-level design scheme,the function design of each sub-module is introduced from the perspectives of module port,control state machine and circuit structure.The data processing module is responsible for all mathematical operations in the algorithm process,and other modules in the system jointly complete the data transfer operation in the matrix transpose operation.FPGA simulation results show that the imaging processing time is 42 ms when the number of image points is 2048×8192.