The Design And Implement Of Core Algorithms Of H.264 Video Coding Based On FPGA

With the development and progress of the society,video surveillance,video conference,video phone,and other real-time video communications applications are playing an increasingly important role in people's daily lives and work.And people's demand of higher quality of the image and more real-time of the video communication system becomes higher and higher.Therefore,the solution of how to guarantee the quality of the video while still have to meet the needs of real-time is a hot issue in real-time video communications.H.264/AVC is a new digital video encode standard that is developed by the JVT organized by both VCEG of ITU and MPEG of ISO/IEC.Its major aim is to enhance the image compression efficiency and to improve the image data in the network transmission.The powerful high-speed parallel computing power of the logic device FPGA and coding algorithm of H.264/AVC video coding standard match to each other very well.The aim of this paper is to design the hardware of core algorithms of H.264/AVC video encode standard based on FPGA,and the hardware logic is implemented with Verilog HDL in QuartusⅡ.At last the simulation and verified are carried out on the platform of QuartusⅡ.Firstly,this paper introduces the new technology features of H.264/AVC video coding standard different from the other standards.Then,the paper analyses and illuminates the intra-prediction,integer transform & quantified and entropy coding of H.264/AVC baseline profile,and tests and compares the affection on the prediction performance of several prediction models on the JM12.4 platform. According to the test results,some of intra-prediction models are cut.On the foundation of deep research of H.264/AVC video coding standard,the hardware logic of the core algorithms of H.264/AVC are design and a new design ofⅠ-frame encoding based on FPGA is presented in this paper.The design uses the basic modules of the H.264/AVC baseline profile,including intra-prediction,integer transform & quantified,entropy encoding.The hardware architecture is design with Verilog HDL.In order to ensure the real-time of the system,all the modules use the 4x4 block as the processing unit,dealing with 16 data at the same time.In order to decrease the complexity of the design,the complicated modules are divided into several simple modules by the modular thinking.In order to take full advantage of hardware,the integer transform algorithm of integer transform and & quantified is optimized,making the performance of the module more better.Then the integrated routing and simulation are carried out on Altera's QuartosⅡ,and the results and hardware resource counsume are shown later.The results indicate that the hardware designs of the core algorithms are feasible with correct working and high real-time performance.The present design has laid a good foundation for the future to further improve the system's performance.