H.264 Intraframe, Interframe Prediction And Transform Module And Fpga Implementation

With the development of broadband and multimedia processing technology, digital video service has gained people's attention greatly.There are many real-time multimedia applications, such as: video conference systems,video monitor systems etc.Although network environment has been progressing a lot, the bandwidth resource is still limited as far as the fast growth of multimedia applications is concerned. In March 2003, the Joint Video Team (JVT) composed by two expert teams published the final draft of this compressed video standard,which is called H.264/AVC agreement of ITU-T or the advanced part of video coding of MPEG-4 of ISO/IEC. It is the new standard of video-compression which can provides higher compressibility and more friendly net interface. For the enhancement of the coding effciencies,the new standard adopts new tools such as multiple reference pictures, variable block-size in motion estimation, quarter-pixel accuracy for motion vector and integer transform etc.Most of these new tools are critical but computationally expensive for H.264/AVC, especially when full search is adopted. So the VLSI architecture is proposed to accelerate the processing speed.In this dissertation, the whole architecture of H.264/AVC is firstly introduced,this section describles a new MB pipelining scheme for the encoder. And then the intra predictor,mv-search and integer transform hardware modules are represented: firstly with regard to the intra module,the hardware architecture of four-parallel reconfigurable intra predictor is designed to support all intra prediction modes.As for inter module,a 2-D hardware architecture is designed which is faster than the 1-D architecture.For the integer transform module, a parallel architecture which contains a transpose registers is proposed to accelerate the processing speed .Thus these modules can save a lot of time and accelerate the processing speed.Then these modules are all actualized by VerilogHDL.Finally,these schemes are all successfully implemented on Xilinx Virtex II pro xc2vp30.