The dissertation derives from the National Science Research Project of research on and design of high performance network processor, the hardcore of which is a 32-bit RISC processor. Memory Management Unit (MMU) is one of important parts of the processor. The thesis is addressed the study and design of MMU in RISC processor, including DMMU and IMMU, which was based on the construction of two 32-entry(4 bytes per entry)fully associative translation look-aside buffers(TLB), and each TLB entry can map a segment (1MB), a large page (64KB) or a small page (4KB). The MMU is configured via the Coprocessor 15 registers, supporting both user mode and supervisor mode, had two primary functions: translation from virtual addresses into physical addresses and control of memory access permissions. Additionally, the DMMU supported the flush-all as well as flush-single-entry operations, while IMMU supports the flush-all operation only.The design of MMU referred in this thesis was divided into two parts: control and data-path. The former part, aiming at the control of performing mode of TLB and abnormities of MMU, was designed in the traditional design way and was implemented by FSM (finite state machine) in RTL with verilogHDL. While the data-path requires high performance, so it was full-custom designed, and TLB (transition look-aside buffer), as a primary part in the data-path, assuming FIFO (first in first out) in replacement algorithm, was designed by CAM-RAM frame. According to the design requirement, circuits and layout were designed, and then the simulation model of data-path was written in verilogHDL. Ultimately, the result of the function simulation testified that the design of MMU could translate virtual addresses into physical addresses and control memory access permissions. The layout of data-path has been designed in the 0.25um CMOS process with almost 65000 transistors in a dimension of 1.41084 mm2. |