Design And Verification Of Embedded Processor Memory Management Unit

The development of multi-tasking application and architecture improvement introduce the need of virtual memory management in embedded processors. Virtual memory management is implemented through a hardware memory management unit (MMU) that supports address translation and protection on the fly. The performance evaluation of MMU in embedded processors is quite different from that of the general purpose processors. First, embedded processors are often used in real-time applications, so worst-case performance is a major concern of hardware designers. Second, power consumption is also an important factor in designing high performance embedded processors.This paper presents a new designing method for CK-Core MMU, CK-Core is a 32 bit high performance embedded processor collaborated by Hangzhou C-Sky Microsystem Inc and Zhejiang University. The CK-Core MMU adopts two-level TLB, referred as Micro TLB (μTLB) and Joint TLB (jTLB). Compared with conventional TLB structure, μTLB has relatively small size and its address translation logic is optimized. The fast translation process makes it possible to use physical cache without adding a translation stage to the processor's pipeline. To reduce miss ratio and power consumption, 48 fully associated entries in jTLB are divided into 6 banks, a selective searching mechanism is adopted, a hardware FSM is in charge of replacing an entry of μTLB based on LRU algorithm if μTLB miss occurs. In case of jTLB miss, a software managed TLB refilling strategy is applied to not only improve the flexibility of page table organization but also reduce the hardware cost.Also, the verification method and flow for MMU are illustrated in the paper, static test and dynamic test can be utilized in different verification stage to help designers to trace the designing faults and achieve high code coverage percentage, this in turn guarantee the quality of design.