A Decoder Of X86 Instruction For ARM-Based Embedded Platform

Traditional computer software is closely dependent on the underlying machine platform, which means program compiled for one machine cannot run on another. With the evolvement of abundant newborn architecture and operating systems, there are greater demands for software transplantability and the inter-operation between computer systems. To solve this problem, Binary Translation technology can translate the binary code of one Instruction Set Architecture (ISA) to another ISA, which can implement software transplantation between different ISAs.With the goal of compatibility and transplantability between x86 and ARM architecture, this thesis firstly study the architecture and instruction of both and then present a Static Binary Translation Algorithm to translate 32-bit x86 instructions to ARM. The core module -Decoder module, implemented with Verilog HDL, can deal with more than 130 instructions. The restrictions of the Decoder module are also given in the thesis. Also a TLB module which can improve the throughput of the whole Decoder by directly output the ARM instructions of matching x86 instructions. At last the decoder is integrated to a ARM7-based SoC successfully. Now there still exist many drawbacks in the design. In the later research, we will optimize the algorithm and implementation of the design and make it run correctly and more effectively.