| BWDSP is a digital signal processor (DSP) designed for high-performance computing. Compatible with16bit and32bit fix point format, using very long instruction word (VLIW) and single instruction multiple data (SIMD) architecture, BWDSP has strong support for parallel computing and real-time applications. BWDSP has4cluster units, each with some computiong components. It has a plentiful set of instructions, which makes opportunities for SIMD compiler optimization.There are two main points in this paper. Firstly, a plantform for instruction decoder verification is designed and implemented. Secondly, a tree-based algorithm for SIMD compiler optimization is proposed and implemented based on Open64compile infrastructure.DSP decoder verification platform is based of BWDSP instruction set, using object oriented technology to verify the continually changing instruction set. The DSP decoder verification platform has good support for reusing and extension. Specific to instruction set variation, a new edition would be implemented in extremely short time.Based on Open64compiler infrastructure, we propose and implement a tree-based SIMD vectorization algorithm. The algorithm works on the high layer of the intermediary language WHIRL. Via a series of analysis and transformation on the inner loop, the compiler finds the chance of vectorization. Then, with the operator in the inner loop matched and replaced with SIMD operator. BWDSP has some special vectorization instructions which are also supported by our algorithm. The compiler recognizes the operators that could be replaced with special vectorization instructions and replaces them in the WHIRL tree. The special operator substitution algorithm supports all BWDSP special instructions including MAX and MEM. the final experiments shows that our tree-based SIMD optimization algorithm can achieve6and4.15times performance improvement for double word vectorization and single word vectorization on average. |
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