Research And Design Of The Digital Baseband Of UHF RFID Reader

RFID is a non-contact automatic identification technology for the object identification。Because of non-contact,being able to identify moving targets,and multi targets,RFID technology has been widely used。Because of longer distance and higher speed identification,the RFID in UHF is the research focus。And a single chip for UHF RFID reader,which can reduce space, power,and bring more efficiency,becomes the focus。As it is very difficult to intergrate RF,analog and digital part into a single chip for one chip reader,the analog and digital part are designed on a single chip,whereas the digital basband part is designed and verified with FPGA。They will be intergrated into one chip in future。In this thesis,on the basis of the UHF RFID reader digital baseband system architecture,algorithms and their relative technologies developed in these fields, the FPGA design and implenmentation of the RFID reader's digital baseband based on EPC C1G2 protocols is realized。The main work of this paper is presented as followed:1.The EPC C1G2 protocol is introduced in detail,on which based on the parameters for this design are set up,the structure of the digital baseband system is presented,and the algorithm,circiut and logic design of every module of the transmitter,receiver,and controller units of tihe digital baseband system are also put on。2.The transmitter unit is improved to accomplish the DSB-ASK,SSB-ASK, and PR-ASK modulations simultaneously。The raised cosine filter is improved to reduce area。3 The receiver unit is modified,where the amplitude detector is added and the sampler is improved so as to get correct value for bad and variable analog signals in low frequency。4 The design is verified in FPGA flow。It is applied in Xilinx Virtex4 series XC4VSX35 enviroment。After downloading the design into FPGA and testing the function,it is proved the targets are accomplished。...