Design And Verification Of The NAND Flash Controller

With the development of the multifunctional mobile telephone, the demand for the capacity of the chip's memory is growing at a phenomenal rate. NAND flash memory has become the preferred data storage solution for many digital products due to its fast access time, high desity, cost/performance and so on advantages. It becomes a tendency that NAND Flash controller is integrated in diversified SOC.The characteristic and differences of the two dominating forms of realizable framework of the Flash Memory are discussed, and the typical storage structures of NAND Flash are analyzed in this paper. The common access manner of different NAND Flash is expatiated . The exact timing criterion of the requirements of these common aceessing operations is discussed also, coupled with the requirement of a certain mobile telephone company's SOC, proposing a realization scheme of the NAND Flash controller which is based upon the AMBA bus.The realization of the controller that proposed in this thesis can support two typical spec of NAND Flash in the market, also, it can control multi-chip which may vary from one to four chips at simultaneously .The configurable timing control mode improved the access time of different devices . In the design of the main-control logic module , a way that so_called " block read" and "block write" is adopted to carried out the "page write" and "page read" fuctions of the big page devices.as a result ,the size which is used as data buffer is significantly cut down ,and the the cost of hardware implementation can be cut down accordingly.To deal with the the problem that the bits stored in the chip can sometimes flip reverse in the process of access operation, the functions that error-checking and error-correcting are be added to the controller . ECC Algorithm is thoroughly analyzed in this thesis, and the realization of the hardware and optimization of the ECC Algorithm is discussed .the fuction is carried out that the high-speed error-checking and error-correcting at real time, without affecting the efficiency of the normal access operation.Two modes of verification is adopted to verify the NAND Flash controller , which are Simulation and FPGA verification. First, a complete Simulation of the whole functions of the controller is made, and the controller works well. Then the FPGA verification is made on the board of Xilinx-Vertex4. The result shows that the controller works properly , it can exactly control the operations which be put into the devices .The controller that is designed and verified in this thesis will be applied to a certain company's mobile telephone's SOC . The method of the implementation of Nand Flash controller proposed in this thesis has a broad practically value in engineering , and is applicable to the general system design and optimization of the Flash memory system.