Study On The Board Level Test Based On Boundary Scan Technology

The complexity of Printed Circuit Board (PCB) is on the prompt increase because of the great improvement of IC technology; as a result, the traditional circuit test methods which use physical probe can not meet the requirement. Boundary Scan Technology is developed to resolve the problem. This paper studies the PCB manufacturing test methodology based on Boundary Scan, including test action development and interconnects test algorithm optimization.Test platform is based on Boundary Scan tool of ASSET Company. Test code for 3 different boards are developed and verified, which include typical boundary scan test process such as scan chain integrity test and interconnects test. This paper also summarizes a few Design For Test (DFT) guidelines with the knowledge acquired from the test development. These DFT guidelines can be used as reference while designing boundary scan circuit, which are useful to improve test coverage and make the PCB test flexible.The board interconnects test methodology based on Boundary Scan is investigated in this paper. Traditional interconnects test algorithms assume that one net can only have one fault. A new complicated defect model has been proposed which assumes multiple defects exist on one net. 2 new adaptive algorithms which have multi-steps have been proposed. The vector generation algorithm for each step is optimized and reverse test methodology is introduced according to Boundary Scan principles. These 2 algorithms can reach maximum diagnosis with less test vectors. The quantity of the reduced vectors is determined by the nets size and defects distributing. An equation about it is provided in this paper.