The Design And Realization Of Multi-core Processor Based On SOPC

With the popularity of the multi-core processor, people pay more and more attention to the development of multi-core technique. How to design the architecture of multi-core processor in order to improve the computers' performance is a topic that is worth researching. There are already many commercial multi-core processors, but there is not an open hardware platform for researching on multi-core processors. This paper aims to design and implement a symmetrical dual-core processor, in order to further study of multi-processor architecture and related technology. It has three main part: single-core processor, shared Cache, as well as multi-core data and instruction bus. Multi-core processors enhance the overall performance by using multiple processor cores to complete tasks. This way breaks the bottleneck of the single-core handling capacity. It's helpful to design and realize the multi-core processor by using simple single-core.This paper introduced how to realize the simple single-core by simplifying and modifying the architecture of OR1200 soft IP core based on further study about OpenRisc series OR1200 Soft IP Core processor, how to design and realize the share-cache on the basis of analysis of OR1200's cache, and how to design and realize the data bus and instruction bus by referencing the idea of Wishbone Bus. According to the architecture of symmetric multi-processor, the dual-core processor is realized.This paper introduced how to use software simulation to verify the dual-core processor. Timing diagram analysis is verified the date bus's and instruction bus's arbitration mechanism and the correct data flow. To verity the single-core's function is correct, using SOPC to build the test platform, and using the codes of register operations to test the single-core. And the functional testing of the dual-core processor is conducted in the end of this paper.The study provided a program of research ideas and reference of the structural design of multi-core processors, and a hardware platform for further study on multi-core processors.