The Design Of Multi-core System Based On Nios Ⅱ　Soft-core

Multi-core processor technology was brought about based on a point of view: improving processor performance only by increasing frequency may increase the power and heat. The multi-core processor technology provides a broader horizon for improving the integration and performance of chips in future.This thesis aims to the realization of the 16-cores system by using SOPC technology. Single-core SOPC and 16-cores SOPC based on Nios II were configured in SOPC Builder. It is feasible to solve communication problems by using NoC in multi-core processor system. This thesis describes the method for solving communication problems between 16-cores in multi-core SOPC with a 2D-mesh NoC and system performance tests. These tests are as follows. We tested the data transferring time with different injection rates (0.0006~0.0018). The test results show that transferring time increased when the injection rate was equal to 0.0012. Then we tested the interrupt latency of Nios II system with 50MHz. We designed a circuit to send an interrupt request to Nios II. Then the Nios II will send a handshake signal back to the circuit. A counter in the circuit recorded the running time of this process and wrote it to the memory. Finally, we simulated the data flow of an MP3 decoder and a 3GPP-LTE 4×2 MIMO receiver in 16-cores SOPC. And data transferring time was recorded.The Interrupt latency is equal to 2.9us. And the ratios of transferring time between actual systems and the Nios II system were 8:3 and 1:476 respectively. So our system could simulate simple system such as MP3 decoder. But applying this system for high performance applications is not appropriate. Since Nios II is the bottleneck, adopting a processor with higher performance but lower flexibility in design instead can surely improve system performance.