High-Efficiency Image Compression SoC System Design And Verification

With the development of micro-electronics technology and semiconductor industry, the integration and technology of grand scale integration circuit have improved obviously. The submicron technology, such as 0.13um and 90nm, has become maturation, which means it is possible to integrate a system on a chip. Namely, this is the System on Chip in modern time.JPEG2000 is the next generation still image compression standard, which is one of the best algorithms of compression performance. In many areas there is a very important application prospects. As the JPEG2000 algorithm complexity is very high, in order to balance processing power and scalability programmability, this paper adopts SoC architectures, using JPEG2000 hardware IP to achieve the core processing functions, using ARM processors to achieve chip control functions.Mainly target of this paper is to finish design and verification of high-efficiency image compression SoC. We have designed bus frame according to AMBA2.0 protocol, and also designed static memory interface, on chip memory controller, interrupt controller, AHB to APB bus bridge and image data transmission module based on AHB protocol, watch dog, timer, GPIO, REMAP and UART module based on APB protocol. Otherwise we have also designed clock module, reset module and JTAG debug module which are the necessary modules on a chip. This system also provides a necessary interface for image processing on the chip, and then we could program arithmetic or control information which is hard for some hardware to do.