Testbench Implementation For AMBA Protocol Conversion Based On UVM Verification Methodology

An advanced verification methodology called UVM with the the practical projectwill be introduced in this paper.These days, with the high speed of the development oftechnology of semiconductor. The ability of designing a integrated circuit has beenimproved rapidly. So the scale of the integrated circuit become more and more and morelarger and much powerful than ever before.Therefore, it is that SOC designMethodology has become a trend of development to integrated circuited.So theworkload of Verification for SoC design has been getting more harder and complicatedand the traditional Verification methodology can not meet SOC design because it ismuch more complex than the traditional integrated circuite design.Thus, UVM isproposed in this paper to solve this issue.The full name of UVM is UniversalVerification Methodology that complemented with many reusable verification method,.In this paper, author adopt UVM combined with practical examples in the projectto explain that UVM can be used to build TestBench more flexible more reused.UVMcan modeling under transaction;evel by signal packaging,build UVC (UniversalVerification Component)follow the dut features.and connect all the UVC together andthe SoC Verification testench has been built.Finally, author run simulation by VCS toolsto analysis the coverage database and the waveform.And come to the conclusion thatuse of UVM to build SoC testbench can save lots of time for verification,and morereused and more flexible.and reduce the cost of SoC verification...