Design And Implementation Of GPS Receiver With FPGA

GPS(Global Positioning System) is now the most widely used global positioning system. It is widely used in the navigation, surveying, mapping, communication and other fields. GPS system includes the space constellation, the ground monitoring station and the GPS receiver. In this paper, we research on and design GPS receiver, especially the baseband processing including acquisition and tracking. And it is implemented with FPGA.Acquisition is a two-dimensional search process of the Doppler frequency offset and C/A code phase for all or part of the satellites. This design choose the parallel code phase search algorithm. To improve the sensitivity of acquisition, we use 10-milliseconds coherent integration and 10-times noncoherent integration, as well as code delay compensation. In terms of hardware implementation, we adopt an improved parallel code phase search architecture, which can partly parallelize the search of Doppler frequency by shifting the signal in frequency domain. Consequently, we reduce the search time of 32 satellites and specific 8 satellites to 1.17 seconds and 0.5 seconds, respectively.Tracking is to synchronize the satellites with more precise frequency and code phase, and to keep continuous tracking. The tracking module mainly consists of carrier loop(also called phase locked loop) and code loop(also called delay locked loop). To improve the tracking sensitivity, we introduce 2 states of tracking including traction state and stable state. In traction state, we choose 1-milliseconds coherent integration, 50 Hz carrier loop band and 8Hz code loop band. The tracking module, which has high dynamic in this state, can correct the remaining frequency offset and C/A code phase offset, as well as find the edge of navigation data(bit synchronization). In stable state, we choose 10-milliseconds coherent integration, 25 Hz carrier loop band and 2Hz code loop band. The tracking module, which has high anti-noise performance in this state, can complete the following tracking process.Finally, from practical test, the cold start time and hot start time of the designed GPS receiver is 28.57 seconds and 1.5 seconds, respectively. The positioning Circular Error Probable(CEP) is 6.5 meters. The acquisition sensitivity is-143 dBm, and the tracking sensitivity is-150 d Bm. It is comparable to the commercial GPS receiver chip----SIRFstar III, even overpasses it in the aspect of cold start time and acquisition sensitivity.