FPGA-based Implementation Of GPS/BD2Multi-mode Receiver

BeiDou Navigation Satellite System, the Global Positioning System, the GLONASS System and the Galileo Position System are called the four great global satellite navigation system. Currently, BD2has been providing services in most parts of Asia. With the increasing popularity of BD2’s applications, BD2receiver and multi-mode receiver combined by BD2and other satellite navigation systems get more and more attention. And the multi-mode receiver with high accuracy, good reliability, etc., is currently a hot research in this field. In this context, the thesis analyzes the implementation of GPS/BD2multi-mode receiver based on FPGA, designs and simulates the baseband processing modules.This thesis divides GPS/BD2multi-mode receiver into three functional modules, ie the RF front-end, baseband digital signal processing, as well as positioning solution. And the baseband digital signal processing is divided into the signal capture and tracking parts. This thesis analyzes the principles and implementations of signal capture and tracking, then selects the serial related searches sliding capture, and delay locked loop methods. The core contents as follow:(1) Design GPS/BD2hardware platform for multi-mode receiver. The platform includes four major parts, ie the RF front-end module, baseband digital signal processing module based on FPGA, the positioning solution module based on ARM9, as well as the expansion board.(2) Design baseband with16GPS channels and16BD2channels in VHDL, and simulate each module and single-channel’s function in ISIM.(3) Debug the SPI interface between ARM and MAX2769, the external bus interface between ARM and FPGA, and the ARM’s UART interface to prepare for the subsequent development.