Research On The Rapid Extracting Algorithm Of Structured-light Seam Image

With the development of automatic welding technology, using software technology to extract the structured-lights information of seam image can not meet the real-time requirements in welding process; while continuous development of the SOPC technology and the FPGA-Chip applications which make using hardware to achieve the welding image processing become feasible. In particular, the application of FPGA chip which is embedded NiosⅡsoft-core processor makes the design of welding image processing system become more convenient, flexible; at the same time, image processing speed has been greatly improved.Based on the development status of domestic and international welding image processing, this paper analyzed the SOPC technology,FPGA development environment and image processing algorithms. The welding seam image processing system had been overall designed. The entire welding image processing system consists of image acquisition module, image processing module, image display module and welding-torch control module; among all the modules, the image processing module which is responsible for implementation of specific algorithms is the focus of the study.The first step of the welding image processing is the image pre-processing to remove image noise and other interferences; the image pre-processing contains large amounts of data requires the demanding processing speed, but its algorithm is relatively simple. FPGA-based image processing system is suitable for image pre-processing. In addition, because of the seam characteristics and image processing requirements, the processing need to extract seam image information and quickly pass the information to welding institutions to control the walking of welding-torch. Prior to carrying out the seam-center extraction, the structured-lights image should be image-processed in order to achieve the desired results.The image processing algorithms of the structured-lights seam include median filtering, thresholding, edge detecting and the extraction of centerline. The median filtering algorithm had been improved in the text, which was designed as a three-point comparator module. Using the module Reuse-Principle, the fast median filtering called the module 7 times, which saved hardware resources and greatly increased processing speed. The edge detection algorithm was optimized by using assembly line techniques and modular design concepts, fully used the inherent parallelism of the algorithm. The algorithms such as binarization, edge detection, the extraction of centerline which usually used software to achieve, but now were written in hardware description language and was generated module, then downloaded into the FPGA chip with Nios II soft-core processor embedded, making it easy for welding image processing called.The algorithms were written in Verilog HDL language, the developing software is Altera's Quartus II 5.0. Through the waveform simulation, the algorithms are correct and feasible, and the system efficiency is much higher. Image processing display showed that welding image processing using the FPGA chip could achieve good results and the processing speed was much faster than the using software method; the welding image processing can meet real-time welding image processing requirements.