Current, Continuous Boost Pfc Chip Analysis And Design

With the development of power electronics, a bulk of power electronic devices are applied, which brings harmonic and reactive power dissipation to the AC line, called harmonic pollution. Power Factor Correction (PFC) is an effective technique for restraining harmonic pollution and increasing the efficiency of the AC line. The Power Factor of electronic devices is a main index to judging their performance, while Active Power Factor Correction (APFC) is a radical and effective approach to improve Power Factor. With the higher quality requirement of electrical equipment, APFC technique has been widely applied.In essence, the aim of PFC is to make the input terminal of electrical equipment appear resistive to the AC line, and insure that the input current be proportional to the instantaneous line voltage. Employing PFC circuit in the front of the AC/DC power supply can set the output voltage higher than the peak value of the AC line voltage. The thesis is from the cooperation with a company. A boost mode active power factor controller is designed based on UMC 0.6μm 30V BCD technology, which uses average current, continuous conduction mode. The controller mainly contains VEA, GAIN MODULATOR, IEA, OSCILLATOR, PFC COMPARATOR, PFC LOGIC sub-blocks and a lot of protection circuits about PFC operation, such as OVP, OCP, Tri-Fault Detect and so on. The total application circuit proposed has these features: 500W output power, 50Hz line frequency, alternating current from 90V to 264V, 400V output voltage, 12V output voltage ripple, 100kHz switching frequency, 0~70℃temperature rage. With 110V AC input, the circuit has 93.8% efficiency, 0.9957 power factor and 5.2% THD, having achieved the design specification.In this thesis, the control strategies of active power factor correction are analyzed and compared firstly. Then, the whole circuit topology is proposed according to the design specifications. Based on that, a 500W active power factor correction application circuit is designed and parameters of external components are calculated. Based on the whole chip function requirements, design and simulation of sub-blocks are completed, including 7.5V REFERENCE, IEA, OSCILLATOR, PFC ILIMIT, PFC COMPARATOR, PFC LOGIC, VIN OK, DUTY CYCLE LIMIT and CLOCK LOGIC. At last, simulation of whole chip function and some typical performance characteristics are presented.On the basis of circuit principle analysis, sub-block circuits and the whole chip circuit are simulated with Hspice. The simulation results indicate that the circuit has achieved the design specification and the circuit principle analysis has been verified.