High-speed Clock Signal Jitter Of The Adc Measurement Techniques

With the increasing of data rates in communication systems, the quality of clock becomes the key factor to affect the system performance. The short-time variation of clock directly works on the index of systems. Timing jitter has always degraded electrical systems. To reduce jitter in system redesign, it is needed to find out the characterization of jitter and identify jitter sources. It's necessary to test and evaluate the clock quality. Some people who are studying clock jitter measurements get that it's possible to deduce clock jitter by analyzing the parameters of the output signal with ADC. Here, the clock under test is the sampling clock of ADC. There are several methods put forward to measure jitter by ADC, such as interference sampling including simple interference sampling and complex interference sampling and SNR measurements.This paper studies the ADC measuring clock jitter technology based on simple interference sampling. The main contents are illustrated as follows:(1) The definition and categories of jitter are introduced, and three sorts of familiar jitter in serial communication systems named as timing jitter, period jitter and cycle-to-cycle jitter are the emphasis. The relation between phase noise and timing jitter are analyzed. A jitter generator is built by simulink and realized by FPGA.(2) The principle of the simple interference measureing jitter is deduced, simulated and validated by MATLAB.(3) While designing the ADC testing hardware system, it's difficult to get a perfect performance sine wave whose phase can be adjusted. In this paper, there are two projects are put forward. At last, the experiment data is collected by the two testing systems, then compared and analyzed by MATLAB.