| A high efficiency peak-current mode synchronous buck regulator IC is designed on the basis of the project "Theoretical research and design of key techniques for power management IC". The whole pre-simulation has been completed using the EDA softwares, such as Viewlogic, Hspice, and the layout design will be finished later.First, a brief introduction of the power management industry followed by a compendious description of the basic topologies and operation of the switching mode power converters is given. Then a system construction is accomplished with respect to the control method, operation mode and main functions. Before the detailed description of the sub-block design, the key technologies of this whole chip design are presented. Finally, part of the whole chip performance characteristics and electrical characteristics are given.By adopting the technologies of synchronous rectification, two operation modes at light load and drop-out operation, the efficiency of XD8104 is up to 96%. In order to prevent the sub-harmonic oscillation at high duty cycles operation, slope compensation is used. A approach to synchronize without reducing the effectiveness of the slope compensation is to implement a phase lock loop (PLL) together with the regulator on the chip.The PLL ensures the voltage on the oscillator's capacitor always reachs the trip voltage as long as the external clock is within it's capture range (1MHz～1.7MHz).Thus the duty cycle information on the oscillator's capacitor is retained. Finally, the circuits for testability are designed to shorten the test time and get more profit margins. |
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