Low-power Fast Transient Response Ldo Design, The Entire Film

Compare low dropout regulator(LDO) to the high cost and output noise switching power supply which uses complex and hard to integrate auxiliary devices, LDO is not only simple, low cost and noiseless but also can be easily integrated. Those features make it preferable for system-on chip design where high quality power supply is needed. Due to the fact that for LDOs on system with limited power source, such as portable devices operated by battery or Radio Frequency Identification (RFID) chip operated by electromagnetic field, quiescent current should be minimized to prolong the low-load battery life or extend the minimum working range, transient response need to be optimized to minimize the overshoot/undershoot voltage due to variant loading current ,which means smaller internal/external filter capacitor can be used to save the precious die-size or area of printed circuit board, great efforts have been put on improving transient performance while keeping low quiescent current.In this paper: first, the basic operating principle of LDO is introduced and a system level model is given to analyze the limit and relationship between quiescent standby power consumption, transient response and feedback loop stability. Second, commonly used frequency compensation and transient enhancement technique is given and analyzed. Then a novel transient enhancement technique: Adaptive Slew-Rate Enhancement Biasing(ASREB) technique is proposed and used to improve the performance of All-in-one regulator with Feed-Forward Compensation (FFC), after verified by simulation, this LDO with ASREB was laid out by back-end engineers and fabricated in CSMC EEPROM 0.13um process, the experiment results showed the proposed technique is able to expand the unity-bandwidth of the LDO ,achieve better loop stability and reduce the output overshoot due to transient load current change. In order to solve the drawback that the output voltage of a All-in-one regulator is process and temperature dependent and direct use of FFC in a two stage opamp based LDO could lead to great performance degradation, a new FFC structure which is suitable for two stage opamp : Virtual Input Stage Feed-Forward Compensation (VISFFC) is proposed and analyzed. With a 0.9nF on-chip capacitor, quiescent current kept at 23uA, a 1.5V,10mA LDO with 0.3V dropout voltage is designed and simulated in CSMC 0.13um EEPROM process, simulation result shows that the overshoot and undershoot of the output voltage are less than 170mV when the load stepping between 0 and 10-mA in 100ns, which is superior to other LDOs employing different compensation technique or topology, the widest unity-gain-bandwidth and best optimized transient response performance is achieved.