Analysis And Design Of High Performance Low-Dropout Regulator

In the survey of Chinese power management IC (PMIC) markets from 2007 to 2009, the Low-Dropout Regulators (LDOs) is at the first place among all kinds of PMIC. The consumer electronics have a large and constant demand on LDOs, since LDOs can provide low noise supply voltage with less PCB area and less power consumption. Besides, the simple topology of LDOs makes them very suitable for the System on Chip (SoC) as an Intelligence Property (IP). But with the changing needs of the market and progress of the technologies, the requirements on LDOs' performances become higher and higher. Less off-chip devices and high power supply rejection become the hot points of research and the development trend.At the first place, the key points of high performance LDOs have been analyzed through system design. Including:the nano-ampere reference current source, the frequency compensation methods, the large-signal response of LDO and the transfer function of supply noise in the closed-loop system. And then several novel circuits implementations have been proposed respectively to those theories:30nA reference current source,3 kinds of pole-zero tracking frequency compensation techniques based on a novel controllable active resistor,4 kinds of slew-rate enhancement circuits and 4 system implementations of high PSRR LDO based on noise cancellation techniques.Based such circuits'blocks, by using CMOS mixed-signal process, three high performance LDOs have been implemented. They are:1) An low power consumption LDO with 3μA quiescent current; 2) An LDO without off-chip load capacitor; 3) An LDO with high power supply rejection (PSRR=-70dB@1kHz). The chip testing results verify the design theory.In the research of nano ampere current reference, the mechanism of the impact on reference current from supply voltage's variation has been analyzed. Thus a novel three branches current reference based on conventional one has been presented. With such topology, the effect from supply noise to the reference current has been depressed. Furthermore, by using the difference of temperature coefficients between two kinds of resistor in the CSMC mixed-signal process and inverse current of diode, the accuracy of reference has been limited within 30±0.6nA in the temperature range of -40 to 130 degree.Since the output pole of LDO can change about 106 times, the most efficient frequency compensation method is to generate a tracking zero, thus the harmful effect from changing output pole to the stability of the closed-loop can be eliminated. In the proposed thesis, a novel active controllable resistor has been presented. With such circuit, the equivalent resistor is more accurate and is less affected by the process variation and body effect.3 pole-zero tracking frequency compensation methods have been proposed base on such active controllable resistor:1) based on miller capacitor with nulling resistor; 2) based on unit gain compensation cell; 3) based on power stage with pseudo ESR.Since the off-chip load capacitor (CL) can filter and stabilize the output voltage, the large signal response of LDOs has been analyzed in order to implement an LDO without off-chip load capacitor. Based on the relationship between CL and overshot of output voltage, a deep analysis shows that the slew-rate of error amplifier is the bottle neck for achieving low overshot voltage. In order to maintain the low power consumption of LDOs, slew-rate enhancement (SRE) circuit has been used to provide extra dynamic current to charge/discharge the gate capacitor of the power transistor. In this way, the large-signal response of LDO has been optimized. In the proposed thesis, there are 4 kinds of circuit implementations for SRE circuits. And in the design of LDO without off-chip load capacitor, a novel SRE circuit based on differentiator has been used, and then the maximum value of overshot voltage drops from VDD to VOUT+0.55V.Although there are a lot of discussions about the power supply rejection (PSR) in the papers or the textbooks, a blank space is still there for the power supply noise in the closed-loop system. In order to fill such gap, the power supply noise transfer functions of 6 basic amplifier's topology have been analyzed. Following the obtained theory of noise cancellation among cascaded amplifiers,4 methods have been presented to improve the power supply rejection. In the circuit's implementation of high PSR LDO, a design plan of canceling the supply noise from first and second gain stage has been used. And according to its poles and zeroes distribution, a frequency compensation method based on pseudo ESR power stage has been introduced into the system. Finally the PSR of-70dB within 1kHz has been achieved.