A Off-Chip Capacitor-Free LDO Design And Research

With the gradual development of the portable electronic products, as well as the direction of multi-functional, low-dropout linear regulator because of its small size, low noise, simple circuit structure and low cost, it plays an important role in the power management chip. The SoC and IP reuse technology for chip integration requirements are relatively high, so how can we get rid of the chip LDO large capacitor to increase chip integration has also been a lot of attention and research. Therefore, no off-chip capacitor LDO study is of great practical significance.This paper aims to develop a high-performance chip without external capacitor LDO.Its wide input voltage range for the 3 ~ 5V. Output current range 0 ~ 100 mA, the output voltage was 2.8V. When VIN is 3.3V,the load transient response overcharge voltage is less than 150 mV. This paper describes the current stability and improve transient response technology without LDO chip capacitors, and then introduced the theoretical foundation part LDO proposed LDO performance parameters. Discussion and analysis of non-chip capacitance stability and transient response LDO Problems On this basis, we propose targeted optimization. This paper is mainly used to optimize the stability of nested Miller compensation to optimize the transient response by adding a slew rate enhancement circuit.Based on research and development for circuit simulation based on CSMC 0.5?m N-well process optimization. Finally, the simulation results were as follows: VDROP minimal pressure drop of less than 200mV; quiescent current IQ is about 60?A; linear adjustment rate LR is approximately 0.073%; LDR load regulation is about 0.03%; and to ensure that when the load current changes the voltage overshoot no more than 150 mV.