Design Of JPEG Decoding IP Core Based On FPGA And Its Application In Digital Watermarking

With the increasing development of computer network technology and the rapid rise of e-commerce, the consequent commercial disputes are more and more. To protect the security of electronic bills, which are the sole basis for the determination of disputes, the digital watermarking technology which takes copyright protection and authentication as the target has been introduced. The electronic bills usually are JPEG image format, so watermarking technique based on JPEG image also become a hot spot.Most watermarking scheme is realized through the software way today, but its speed has been limited. Based on the study of the status quo JPEG format image watermarking technology and IC development, the custom JPEG decoder IP core is designed combined with SOPC technology, and it will be applied to the watermark embedding scheme on FPGA platforms. Considering the IP core’s reusability, and the JPEG decoding technology is the foundation of other encoding formats (such as MPEG, etc.), the JPEG decoding IP core can be applied in more complex image processing system, which can also be embedded video watermarking technology to provide a reference value.In this paper the digital watermarking algorithm deep into the field of integrated circuits combined with the JPEG image watermarking processes and SOPC technology, Verilog HDL language is used to design and implement of a reusable JPEG decoder IP core which can be embedded, realizing the JPEG decoding on FPGA platform and further completing the watermark embedding. The JPEG decoder is tested through the Modelsim simulation software and would be revised until the simulation results become correct. Finally, the Altera development board EP2C70F896C6N of Cyclonell series is used to complete the system design. The results prove that the system can run well, the program which can obtain a larger increase speed in exchange for consuming a little hardware resource does work.