The P1750a Processor Data Path Design

This paper mainly discussed the integration of 1 750A system, and the high level design (HDL) methodology was used to implement it. It analyzed every step of the integration and the design flow of this methodology, with a focus on the design.Firstly , the analysis of the 1750A system and the MIL-STD-1750A instruction set was described ; then design of the system control path was discussed, which included the design of execution FSM and micro-controller.; later the datapath design was described in detail, the design of function modules in the datapath was discussed, such as ALU, address processing unit , bus interface unit ,interrupt and fault controller, register file and timer.After the integration, we developed testing programs to do the functional simulation of the whole system, then the timing simulation after place and route.. Then the system was implemented in FPGA device. After implementation, the system was test by the monitor program, which was developed in 631 research institute. The test result shows the system has implemented all defined function and realized all the requirement.1 750A is a complex digital system. This paper has contributed a lot to the complex digital system integration and the FPGA system design.