Voice Compression Codec System Hardware Design And Implementation

This paper accomplishes the hardware design and implementation of a speech compression system . The system adopts an advanced specific speech compression chip based on AMBE algorithm. It can achieve high compression rate at 4 Kb/s .The system first performs A/D conversion on analog speech input to obtain PCM signal and the PCM signal was encoded by the main compression chip. A FPGA is used as the controller, performing the necessary processing such as eliminating the head of the encoded data frame, storing the speech data into FIFO and transmitting it. At the receiving end, a inverse process is performed .The system receives low rate data and the FPGA reorganizes a frame of data which is decoded by the compression chip every 20 ms. The obtained PCM signal is performed D/A to restore the analog speech signal. The system is full duplex. This paper first introduces the basic knowledge, current standards and some typical compression algorithms. Then, some analysis of the structure and principles of the system were given. With these done, the control programme is compiled and simulated. Finally, the circuit board is designed and the hardware debug is performed. The following tasks are done by the author: 1. Consulting reference materials, choosing the main compression chip, the control chip and other devices2. Getting familiar with the features and parameters of the chips, determining the structure and scheme of the system3. Compiling and simulating the control programme of FPGA with the software Foundation and analyzing the result of simulation 4. Designing the circuit board with the EDA software Protel, downloading the control programme and completing the hardware debug5. Analyzing the waveforms and evaluating the practical effect of the system...