A Hardware Implementation Of Low Bit Rate Voice Transmission

Today , the resourses of frequcency bandwidth become more and moreexiguous because of the high-speed development. People make a lot of efforts tocompress the transmission channel frequency bandwidth or to reduce channel datarates.As regards the situation of domestic research on speech processing, there is fewdesign which code rate below 4Kbps with good voice quality. Overseas, the researchof speech compression has achieve great improvement ,but the application of low-bitrate speech communication system on all kinds of area ,inluding security and satelliticcommunication, is not sufficient. The design of 2kbps which the thesis has depictedhas its application value and meaning. It can be applied to many domains such aswireless communications, VoIP, secure communications.This thesis accomplishes the hardware design and implementation of a speechcompression system. It also implement the TDD (Time Division Duplex). The systemadopts an advanced specific speech compression chip based on AMBE algorithm. Itcan achieve a lot of compression rate and it can get the max compression rate at 2kbps.The system first performs A/D conversion on analog speech input to obtain PCMsignal, and the PCM was encoded by the main compression chip. A FPGA is used asthe controller. It perform the necessary processing such as eliminating the system headof the encoded data frame, adding channel frame head and storing the speech data. Atthe receiving end , an inverse process is performed to restrore the analog speech signal.This thesis first introduces some typical compression algorithms. Then , some analysisof the structure and principle of the system are given , placing emphasis onintroducing the speech compression chip. Whereafter, the control program is compiledand simulated. Moreover some improvements are given. Finally, the hardware debugand analysis also are given.