Rs Coding-decoding Algorithm And Its Hardware Implementation

This paper mainly discusses how to guarantee information's reliable transmission in a type of SSR system. Proper channel-coding scheme is designed to decrease error-rate in digital transmission.Error-correcting codes work by adding extra information to original data. Among the linear block codes, RS code is an important one widely used in modern digital communications, which can correct both random and bursty errors with the most powerful error-correcting capability.In this scheme, RS code is selected as the main error-correcting code. Its encoding/decoding algorithms and hardware implements are researched. Improve on algorithms can enhance encoding/decoding performance. With pipeline and systolic array architectures adopted in the hardware implements, encoder/decoder based on FPGA can work better. Although this scheme lays more emphasis on RS(31,15), it also considers the parameters' programmability of RS code, which can expand its applications.In this paper, firstly, we introduce the relevant background and the coding theory. Subsequently, we present the error-correcting scheme in this SSR system and elaborate on RS encoding/decoding algorithms and then simulate the selected codes' error-correcting capability. Finally, we implement RS codec with FPGA technology and the experiments show that desired targets can be achieved.