Multimedia Image Processing, Reconfigurable Processing Element Design

The increased use of multimedia applications has significantly increased the computing demands placed on processors. Reconfigurable systems are computing systems that combine a reconfigurable hardware processing unit with a software-programmable processor. These systems allow customization of the reconfigurable processing unit in order to meet the specific computational requirements of different applications. Reconfigurable computing represents an intermediate approach between the extremes of ASIC's efficiency and general-purpose processor's flexibility, promising a valuable alternative to the multimedia processing.Based on the reconfigurable computing system, the thesis proposes RAC, a reconfigurable array coprocessor model, targeted at multimedia image applications. Then, the work mainly deals with the design of the reconfigurable processing element, and evaluates its performances.The research work of this thesis mainly includes: Proposes RAC, a model targeted at multimedia image applications with inherent data-parallelism, high regularity, and computation intensive requirements. The RAC model couples a multi-context, coarse grained, 2-D meshed, and SIMD computation array as a coprocessor to a CPU core. Analyze the design targets of RAC contexts according to the characteristics of multimedia image applications, and presents the RAC context system. Design the architecture of Reconfigurable Processing Element, which supports the implementation of RAC contexts. The major functional units consist of MAC, ALU, and Shifter etc. The units customize the functional units according to the context programs. Design the details of the major units of RPE data-path, with the emphases on the design of MAC and ALU units. Research of some important algorithms of video compression mapping on the RAC model, and evaluate the performances of RAC model.