Soc Hardware And Software Co Insurance Card System Design And Experimental Validation Studies

With the rapid development of the semiconductor process and relevant technology, beyond the traditional integrated circuit, system-on-a-chip (SOC) is coming up. It consists of a lot of intellectual property (IP) blocks and embedded processors, which require a piece of embedded software code to be composed .With design complexity beyond the traditional chips,verification difficulty is growing up. Both hardware and the embedded software should be verified together, the performance of simulator decreased dramatically. As a result, functional verification has become the dominant resource issue in developing SOC. In principle, several years may be required to complete the verification task of SOC. To shorten time-to-market and speed up the verification process, SOC software/hardware Co-Emulation system has been introduced. It splits the SOC Design into sub-blocks, some blocks are emulated in the programmable logic devices, and the rest part is simulated in the hardware simulator, every part of them cooperated with each other.After the IC verification technology is discussed in detail in the thesis, the study of SOC verification technologies and methodologies are highlighted, which include the cutting edge transaction-based verification technology, software/hardware co-simulation, hardware accelerated verification technology. A full implement scheme of SOC software/hardware co-emulation system is given, including the communication protocol between software and hardware, data format, synchronous mechanism between software and hardware of different emulation modes. Co-Emulation mode and Vector Mode are implemented using the C++, Verilog HDL and VHDL. An experiment has been done to prove that the system can work correctly. Co-emulation speed is also tested.In the co-emulation mode, a part of the design is simulated in the hardware simulator, the rest part of design are emulated in the reconfigurable system, two part of the design work cooperated to accelerate the verification speed. In the vector mode, all part of the design is implemented in the reconfigurable system; stimulus and response vector is transferred serially to and from hardware. This mode improves the verification...