Coverage-oriented Verification Of Research And Application Of The Method

With the development of modern IC design, the scale of chip increased exponentially and the function within one chip becomes more and more complex which makes the verification job supper formidable. Functional verification has become the bottleneck of large-scaled chips design.Some new verification techniques came out in recent years. E.g. functional coverage, constrained random stimulus, formal verification, transaction-based verification method and etc. Nowadays, the point at the verification flow is revolves around how to make it more systemic and more structural.CDV(coverage Driven Verification) is a new verification method which can improve the efficiency of testing obviously with it's natural thinking model. It bases on the structural verification method, support constrained random stimulus and the result will be checked automatically. With coverage report as the criterion of verification integrity, it dominants the whole scenario in validation and make the design more reliable. Almost all the EDA vendor has dig into it and coverage statistics has been supported by the mainstream tools.This thesis will analyze the CDV in detail, summarizes the factors of the method and the verification environment. And then apply it in the verification of Virtual Output Queue (VOQ) module. Create the functional coverage model for VOQ and generate stimulus base on the coverage report. We summarize the difference between traditional verification method and CDV with experiment at the end of the article.With popularization of the verification languages such as System Verilog it deserved to be a major verification mythology in a few years.