Based On Risc Architecture Microcontroller Ip Core Design

The design for IC(Integrated Crcuit) has already reached into the level of designing a SOC(system on chip). However, with the increasing scale of SOC,the problem is not whether a chip is able to accommodate to the design for a complex system, but how the design catches up with increasing speed of complexity for designing a chip and meets requirements that the fierce market competition is strict with the time that products come into market. Nowadays, a design based chip cores becomes a trend towards the EDA development . It is promising to develop IP(Intellectual Property) cores with independent intellectual property right. The IP core can be set different function by programming with software, and used in various embedded MCU system.During the systematic architecture, instruction system and systematic timing of PIC16C65 MCU of Microchip were analyzed deeply,the MCU whose the systematic architecture such as time architecture and space architecture is different and instructions were compatible with PIC16C65 have been designed. The design change two level instruction pipeline of divided time of PIC16C65 to three level instruction pipeline of not divided time and overpass improving on HARVARD architecture with 14-bit instruction length and 8-bit data length make one data bus to double data bus such as source data bus and detition data bus so that control architecture is simplied and data operator is quick moreo In addition two periods are used to complete the manipulation of read and write to SRAM in pic16c65,but in this MCU only one period is used.the measures above avoid the possibility of read and write to the same ROM's address.According to system level design methodology from top to down,utilizing verilog HDL for describing in RTL,the IP design of RISC MCU have been finished. after code finished test program in verilog HDL is writed ,by utilizing EDA tool the IP is simulated in fuciton, synthesizing and simulated in timing ,then when design is in hardware verified with XILINX FPGA device. overpass hardware verifying with FPGA, simulated, synthesized and verified with some EDA tools. The results showed that the MCU IP core can correctly execute all instructions and meet the performance of PIC16C65.This paper has contributed a lot to the design of the more complex RISC MCU Simultaneously, it has given the way to the design of SOC based on MCU core.