Design Of Convolutional Neural Network SoC Based On RISC-V

Convolutional Neural Network(CNN)is a widely used deep learning model,which can effectively extract the features of high-dimensional data and realize complex pattern recognition and classification tasks.CNN usually has a large amount of computing and storage capacity,so traditional Central Processing Unit(CPU)or Graphics Processing Unit(GPU)cannot simultaneously meet the application requirements of high performance,low power consumption,and low cost.Therefore,the dedicated hardware accelerator for CNN has become a research hotspot.The main work of this thesis includes mathematical model construction,algorithm verification,architecture lightweight,hardware design,board level deployment,ASIC implementation and so on.Pytorch was used for parameter training of YOLOv5s framework,and the training results were analyzed and evaluated.Matlab was used to verify the algorithm flow,and the framework parameters were quantized to plan the hardware circuit architecture of the neural network accelerator.To deploy the lightweight model,a System on Chip(So C)based on RISC-V is designed and implemented.The So C is composed of Neural network Processing Unit(Neural network Processing Unit,Neural network Processing Unit,NPU),video stream interface,data stream interface and off-chip memory interface module,the system uses AXI4 bus as the system bus,support single and burst transmission.Video streaming interface including OV5640 camera driver interface and HDMI driver interface,for real-time saving and display images;The data flow interface includes SD card driver interface and serial port driver interface,which is used to transmit neural network parameters when the system is started.The NPU includes neural network accelerator modules and a lightweight RISC-V processor core.The neural network accelerator uses pulsating array as the core acceleration structure to realize two-dimensional pipeline acceleration.RISC-V processor core is independently designed,as the system master,supports RV64I instruction set,adopts five-level pipeline architecture,and supports RT-Thread operating system.The simulation results show that the NPU peak computation rate is 320 times higher than that of serial processing at 100MHz clock frequency,and the ideal predicted refresh rate is more than 2FPS.Based on the 180nm CSMC process,the ASIC process of the NPU module is designed and the circuit layout is generated.The layout area is 47082μm~2 and the power consumption is 204.4m W.The SoC was deployed on the Xilinx FPGA platform for board-level verification,and the whole board level system could work normally at a frequency of100MHz,the predicted refresh rate of the board level system was higher than 1FPS,and it had the capability of real-time target detection.The RISC-V processor core independently designed in this thesis has successfully streamed and worked normally in the third"Core for Life"program,and the working frequency can reach 100MHz.