The Fibre Channel is logically a bidirectional point-to-point serial data channel, structured for high performance capability. For its high-speed, high-reliability, scalability and flexibility, it is developed in right response to increasing need for high-speed, high-volume data transfers in storage and network services.Firstly, this paper analyzes the principle and functions of DC-balanced 8B/10B code of Fibre Channel's FC-1 level in detail, and also concludes the internal relationship between coding mechanism and Disparity attribute. As a result of above analysis, it lays out a new algorithm for 8B/10B code's IP core design. The encoder consists of data character encoding, control character encoding and Disparity operation modules, so that it not only improves the encoder's timing performance, but also raises its structural flexibility which will have more outstanding advantages in multibyte parallel encoding. Similarly, the decoder is divided by four submodules, such as data character decoding, control character decoding, error character detecting and Disparity verification, but the two latters are much more complicated. Besides, it also accomplishes CRC's hardware implementation, which is used to improve the performance of data integrity check as a complement to 8B/10B code.All of the hardware modules above are realized by VHDL code, synthesized and simulated by DA (Design Analyzer), Quartus-II and Modelsim, etc. It also makes detailed analysis of implementation results of different hardware architecture, such as parallel architecture and pipeline architecture, etc. Finally, it proves that the new algorithm has more powerful flexibility and error-checking-capability, and can fully meet Fibre Channel's high-speed transport standard. |