Pci Express Switching Device Ip Core Design And Research

The third generation I/O interconnect PCI Express was developed to overcome the bandwidth limit of PCI Bus. It has been at least 10 years since PCI bus was first developed and announced. It employs shared bus topology structure. And in that mode all of devices are connected to one bus, so they share the band width. However, with the development of devices, so many devices need more bandwidth. Then the bandwidth is forced to be improved. But, the PCI 2.2 or PCI-X bus with parallel bus implementation cannot be easily scaled up in frequency or down in voltage because its synchronously clocked data transfer is signal skew limited and the signal routing rules are at the limit for cost effective technology.PCI SIG announced the PCI Express as the third generation I/O system, which adapts present new technology high-speed, low pin count, low voltage differential signaling environment of between 0.8 and 1.2 volts, and point-to-point technologies for major bandwidth improvements. Being different from PCI, it connects devices by switches. So by this way, devices get their own link and bandwidth. Its topology fabric is composed of point-to-point Links that interconnect a set of components, where the switch is playing a very important role.This article can be divided into three parts: theory, design and simulation.In the first part, the specification of PCI Express will be introduced in summary. The theoretical knowledge of transaction layer and switch will be described theoretically in brief, such as PCI Express layers, pockets, fabric topology, transaction types, configuration space, virtual channel, address spaces, transaction routing and interrupts.In the second part, the system level design of transaction layer module and switch module is discussed. According to the function, it is divided into virtual channel receiver, virtual channel transmitter, virtual channel arbitrator, configuration space, router, port VC buffer, port arbitration, etc. The pinch point is the virtual channel arbitration, which needs to support both strict priority VC arbitration and Weighted Round Robin Arbitration for low priory VC, while the VC ID of virtual channels is not hardware fixed but it can be configured by software. In order to support this function, firstly the biggest requiring VC ID is selected to compare with the Low Priority Extended VC Count. So by this way the priority of the biggest VC ID is known. And then with VC arbitration capability the next allowed VC is determined.In the third part, RTL simulations and verifications of sub and top modules were done with Modelsim. And a configurated design was also synthetized by Syplify. At last the simulation results, area and timing report are shown.