Design And UVM Verification Of The Non-blocking Switch Core Module In PCIe-based Switch Chip

With the popularization of the Internet,the rise of big data,and various application scenarios emerging in an endless stream,the information interaction of large user groups and large amounts of data has put forward higher demands and requirements for data transmission.As a full-duplex,high-bandwidth,highspeed differential serial end-to-end transmission interface,PCI Express has been recognized by the market as soon as it was introduced,and has been the factly preferred interconnect for nearly two decades.The main research objects of this subject are switch chips based on PCI Express bus standard and Universal Verification Methodology.This thesis designs a high-speed switch chip that follows the PCI Express3.0 protocol and is forward compatible with basic features such as non-blocking,low latency,and high bandwidth.It focuses on the design and implementation of Switch Core module in the switch chip,and completes functional verification by building a UVM-based PCIe verification platform,decomposing DUT-related function points and writing test cases.The Switch Core implementation includes storage buffering,scheduling and sorting,routing switching,and flow control management of PCIe data packets.It adopts Combined Input and Crosspoint Queued switching structure based on Virtual Output Queue to avoid Head-ofLine blocking while meeting bandwidth requirements.The Switch Core adopts distributed scheduling algorithm and shared cache mechanism to simplifying the scheduling algorithm while reducing the cache area.UVM is currently the most popular verification methodology in the industry.It is based on the System Verilog class library and has reusable components,which can quickly build a verification platform environment with a standardized hierar chical structure and communication interface.In this paper,the reusable important components of the PCIe verification platform based on UVM mainly include monitors,shunts,reference models and scoreboards,etc.,and the switch core completes functional verification in the verification environment.This article will focus on the PCIe Memory bus transaction verification,and analyze and explain the key functional verification points,their test cases,and simulation waveforms.After the VCS simulation,the final DUT achieves pass for all test cases and 82.95% code coverage.At the original bit rate of 8.0 GT/s,the pass-through delay of transmitting 128 Bytes of data is 43.802 ns,and the load bandwidth of the x4 link can reach up to 3627.7216 MB/s.After inspection and review,it meets the verification requirements and achieves the established design goals.The RTL code can enter the next development process.