Design And Verification Of The IEEE1394 Transaction Layer

IEEE1394 is a high-speed serial bus standard which supports asynchronous and isochronous transmission mode. As a high-performance bus technique generally accepted and widely applied to multimedia field originally, IEEE1394 has the features of flexibility, extensibility, high-speed transmission capacity and good real time ability. So far, many electronic products such as digital cameras and high-speed external hard drivers, have adopted IEEE1394 bus interface as well as PC.As we know, Apple Corp first proposed and realized IEEE1394, in addition Sony and TI Corp in the early days also realized and separately named the bus. Up to now, the application of IEEE1394 is not only confined to the civil electronic products, and it has been used in aircraft and other military products.On the basis of in-depth research on IEEE1394, the transaction layer IP core is designed without conflicts with IEEE1394 standard. In this thesis, the transaction layer service is simplified combined with practical engineering need, so that the data transmission can be efficient and convenient, and avoid the abnormal situation. This design of transaction layer IP supports isochronous transmission, and realizes independent isochronous channel to avoid the interference with the asynchronous channel. Isochronous channel has independent buffer and FIFO for data transmission. The transaction layer IP-correlated modules are designed with the core of transmitting channel and receiving channel. The RTL design consists of register controlment, transmitting channel and receiving channel modules. According to the communication modes that IEEE1394 supports, the transmitting channel is divided into asynchronous and isochronous channel, and so is the receiving channel. In this thesis, the sub modules of each channel are divided, the functions of which are defined. Both the sending and receiving process are described, the data transmission states of each channel have been also designed. Correspondingly the register controlment module should be divided into three categories, one for channel management, and the others for controlling the channels.This thesis also proposes a verification strategy based on module level and system level in consideration of the complexity of this design and the necessity of verification. After long-term exploration of various verification methods, the module level verification based on the traditional verification method, with components built by verilog that is similar to UVC, is proposed so as to achieve more automated verification platform and shorten the period of verification. In the module verification, the code coverage data is gathered and analyzed, extra testcases are generated to test the functional points uncovered, and some functional points have to be tested in system level. Considering the correlation between protocol layers, the system level verification on the So C should be carried out to test the data communication. The verification environment consists of the external memory model, the physical layer model, the data comparison model, the universal verification components of the transaction layer and link layer. The system level verification is based on virtual prototype method, and functional models are built according to UVM.The verification result shows that the design meets the IEEE1394 protocol. This design can be connected to the link layer and PHY layer that is consistent with the protocol to constitute a complete So C.