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Bram In The Fpga Design

Posted on:2010-05-11Degree:MasterType:Thesis
Country:ChinaCandidate:R WangFull Text:PDF
GTID:2208360275483322Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
With the development of micro-electronics technology and the improvement of integrate circuit(IC), the integration of digital IC is becoming larger and larger,among them,Field programmable gates array(FPGA) is used today widely. FPGA is developed based on programmable array logic(PAL), generic- programmable array logic(GAL) and erasable programmable logic device(EPLD). As the half custom IC in the field of the Application Specific Integrated Circuits(ASIC), on one hand, FPGA solves the disadvantages of the custom IC, on the other hand, FPGA conqueres the limit of gate number brought by PLD. FPGA is widely used in the fields of communications, data processing, networks, instruments, industry controlling, military, aviation and et al.In this paper, the FPGA and programmable memory block(BRAM) are mainly discussed. The FPGA is the IC device that is programmed by customers to achieve different logic function. It includes input/output Block(IOB) and configurable logic block(CLB). Both IOB and CLB are interconnected by interconnect route(IR). Once BRAM is programmed, it can achieve memory function. BRAMs lie in rows in FPGA. And BRAMs are main parts for FPGA to achieve memory function and they are real RAM which has two read/write ports. Each RAM contains 4096 memory cells and each port has its own independent control signals and each port can be programmed to have specific data width,for example, such as multiplying 4096 and 1 or 2048 and 2 or 1024 and 4 or 512 and 8 or 256 and 16. Thus, BRAMs offer conversion to in-line bus of different width. Each BRAM lies in rows and along with the vertical side of the chip. The height of the row is the same as the device. Each BRAM is four times of the height of a CLB.This paper is a part of the project from the hua wei electrons system company. The designed FPGA in this paper is based on SRAM which has millions of gates. Based on BRAM, we make full use of Verilog HDL and ISE9.1i, together with EDA softwares, such as Modelsim SE 6.1f, Synplify 7.6 as well as Synplify Pro 7.6 to achieve above functions. Then the design are performed the emulating and verification. The requirements are satisfied. It is important for us to break through the monopolization and have our own design for PLD. The design lays a great foundation for products.
Keywords/Search Tags:Integrate Circuit, Field Programmable Gates Array, SRAM, BRAM
PDF Full Text Request
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