Validation, Based On The Scheduling Of Packet Transmission Traffic Management Chip

As the rapid development of semiconductor technology, chips with complicated function, huge scale and high integration density have become the mainstream. With the continuing increase in chip scale and design gates, verification has become the main bottleneck in chip development. How to guarantee high efficiency and sufficiency is the key factor to the successful development, which is also the main study direction for now. Complying with the requirement of the project, the simulation of traffic managing chip with ten million gates in chips of packet transport networks is executed in this subject.The build of testbench and the implementation of simulation are studied in this subject. With the aim of the correctness of chip specification, the sufficiency and efficiency is deeply considered from the verification methods, the general verification course, the particularity of traffic managing chip, and so on.1) Verification methods:â—‹1 to enhance the sufficiency, the method to decompose verification specification is adopted;â—‹2 to improve the efficiency, the layered verification structure is adopted and code coverage is taken as the verification technology.2) General verification course:â—‹1 to boost the abstract degree of the verification environment, interface is adopted to encapsulate the signals between DUT and the environment, translating the reference of several signals to one interface;â—‹2 to match the requirement of different testing steps, the direct and random generation with optional payload type is provided;â—‹3 for the convenience of checking simulation results, the correctness of packets is judged and these results are centralized at the end of the log;â—‹4 to improve the rate of orientating problems, the disorder checking mechanisms for flow queues and port queues are supplied separately and the check of the correctness of packets is divided into two parts;â—‹5 simultaneously, the print of message is controllable for the different requirement of different simulation steps.3) Particularity of traffic managing chip:â—‹1 for the testing of schedule, the rate of generating packet is controllable and the traffic checking mechanism, with movable time window position and adjustable widow length, for the flow queues and port queues are separately provided;â—‹2 simultaneously, to advance the automaticity of simulation environment, the burst of shaping is deleted automatically;â—‹3 to enhance the reliability of the simulation results, the back press of DUT is checked and responded;â—‹4 for the convenience of observing scheduling result, the layered display mechanism of traffic is supplied, in which not only the traffic of subscribers is showed but also the service is showed based on subscribers.The significance of the work is that the thinking of verification flow and deep consideration of efficiency and sufficiency not only guarantee the successful verification and supervise the one-time success, but also provide important cases to the following chip developers. Simultaneously, the methods and thought for the verification of traffic scheduling algorithms throw light on the chips of the same sort.