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Improved Yield Flip-chip Solder Bump

Posted on:2010-11-27Degree:MasterType:Thesis
Country:ChinaCandidate:Y L PanFull Text:PDF
GTID:2208360275991824Subject:IC Engineering
Abstract/Summary:PDF Full Text Request
The current advanced packaging,not only serve as a protection IC or transmission of electronic signals to connect,but also take part in deciding the function of high-functional IC and cost.Package size is gradually developing from chip scale package to wafer level chip scale package.Flip chip with bumping technology can provide the performance of high speed,has become one of the popular packaging technology.A bump connects chip and substrate in Flip chip assembly process.It usually is produced by evaporating,solder paste printing or solder plating process. Under bump metal works as adhesion layer,diffusion barrier layer and wetting layer.The stresses show some variation for different metal materials and process parameter.It will impact CP test yield directly. This thesis focuses on the low yield issue for flip chip Sn/Pb bump wafer. Did serial experiments to find out the root cause of low yield.Al/NiV/Cu UBM instead of Ti/NiV/Cu or applied RF bias of UBM sputter process can reduce the stress and raise the CP test yield.RF bias was found to significantly reduce Ti/NiV/Cu UBM stress.Using NiV deposition with 180W RF Bias,Ti/NiV/Cu stress drop the non-use of RF 1/3.The stress curve of Ti/NiV/Cu Stack Layer without RF bias shows the non-uniform distribution from edge to center.This is why the first trial lots have some specific pattern in the CP map.The stress curve of Ti/NiV/Cu Stack Layer with RF bias is flat.This also states the process of NiV with RF bias can significantly improve the chip uniformity of thin film stress.The stress of Ti and Cu without RF Bias show the little change before and after the sputter,but the stress of NiV without RF Bias is relatively large change before and after sputter.When the RF Bias application,two stress curves of NiV are close before and after sputter.This is not only manifested in NiV stress curve,also reflected in the Ti/NiV/Cu stack stress curve.Therefore,the stress control focuses on NiV for Ti/NiV/Cu UBM,only NiV need to be RF Bias.The same conditions in the production process,Al/NiV/ Cu UBM stress is smaller than Ti/NiV/Cu UBM stress.R & D person not only need to check bumping yield via scan surface defects(2D Yield),also need to check CP data to decide qualification or not.UBM thickness,UBM etch rate,bump height,bump diameter,bump void, bump shear,reflow temperate etc.are monitored during the bumping production process.In addition,it is necessary that control stress. Stress directly related to the CP yield.
Keywords/Search Tags:Flip Chip, Bump, UBM, Sputter, RF Bias, Stress, Yield
PDF Full Text Request
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