Aac Decoder Synthesis Filter Bank Design And Realization

MPEG-2 AAC, a higher quality multichannel audio coding and compressing algorithm, provides exceptional compression radio and thus achieves lower bit rate. AAC has the highest audio quality than MP3, AC-3, and PAC audio coding systems at the low bit rate and fulfills the ITU-R requirements for "indistinguishable" quality at bit rates of 320kbit/s for five full-bandwidth channel audio signals. The rebuilt timbre achieves "transparency" level at bit rates of 128kbit/s for two channel audio. AAC becomes more popular in HDTV-audio, DVD-audio, mobile audio and online audio. As a result, AAC will become one of the most popularly adopted audio formats in 21st century.The dissertation is to design and implement filterbank for software/hardware based MPEG-2 AAC decoder. This module consists of an inverse modified discrete cosine transform (IMDCT), and a window and an overlap-add function. As the hardware accelerator of the decoder, IMDCT is designed in the form of IP core, and realized based on FPGA. As the software of the decoder, window and overlap-add modules are designed and realized based on the audio-specific DSP. Finally, the filterbank is applied in the software/hardware based MPEG-2 AAC decoder, which completes real-time decoding based on the SOC software/hardware co-verification platform. The rebuilt timbre of the decoder is good.1. Analyzed the algorithm, composition and structure of filterbank, built the simulation model based on Matlab software and used high level language to finish the system-level design of the filterbank.2. Did the selection and improvements of the IMDCT fast algorithm, designed and optimized the hardware structure of the IMDCT, used Verilog-HDL language to write the RTL level of the IMDCT, implemented the IP circuit based on FPGA.3. Verified the filterbank based on the SOC software/hardware co-verification platform, analyzed the speed, area and decoding quality of the design. 1. Proposed a new pipeline butterfly unit for AAC software/hardware decoding system and realized 256-point and 2048-point IMDCT hardware accelerator based on the one butterfly unit.2. Compared with the three lately published IMDCT implementations, the proposed design took the minimum computing latency, and required the lowest memory storage.3. The proposed design is based on reusable IP core technology, fits for MPEG-4 AAC and DRA audio decoding SOC application.