Fpga Interconnect Structure Design Assessment Tests

The manufacture costs of ASIC products become much lower along with the rapid development of semiconductor processing; however, the non-recurring engineering cost increases a lot. Compared to ASIC, the unique reconfigurable technology of FPGA can not only decrease the development risk and cost of digital system, shorten the time to market, but also effectively lower the maintenance and upgrade costs by dynamic and remote online reconfiguration technology. Therefore, FPGA is widely used in communication, consuming electronic products, military industries and etc.Among the research and work of FPGA architecture, the design of interconnects architecture is the most important, for it occupies approximately 80% of the chip area and 60% of the signal delay. FPGA routing architecture exploration based on the concept of "general switch box (GSB)" is proposed to improve the performance of FPGA architectures. Compared with CB/SB routing architecture in VPR and CS-box architecture, GSB architecture optimization space is much larger. Experimental results with MCNC benchmark circuits show that the performance on FPGAs of GSB architecture is 24.3% better on average in terms of product of channel width and delay with 0.17% less routing switches than CB/SB architecture of the same segment distribution. In addition, with the two types of wire segment architecture, GSB architecture achieves a reduction by 17.3% compares to the best two types of wire segment CB/SB architecture, and only a 6.32% increasing in switch number.As the rapid growth in adoption of FPGA, testing of FPGA becomes increasingly important. This paper presents an automatic test configuration generation method based on TPG and ORA. In addition, to solve the fault coverage problem, this paper proposes an automatic test-configuration-generation method to test and diagnose faults in FPGA interconnection resources. By constructing routing resource graph and searching all nodes of the graph by direction, the proposed method generates total and partial configurations and then uses JTAG boundary scan chain to apply test vectors on them and readback results. Small number of configurations is required to cover all stuck-on, stuck-off faults in PIPs, open, all stuck-at faults in segments and all bridge faults between segments connecting to the same switch matrix.