Low Power SRAM Design Based On Data Retention Voltage (DRV) Scheme

Static random access memory (SRAM) plays a critical role in state-of-the-art SOC products due to its high speed, robust reliability and integrablility with logic circuits. Simultaneously, SRAM occupies increasingly larger area and power consumption of SOC devices with technology scaling. Therefore, fast and low power SRAM designs have attracted considerable attention. As the technology scales down to 90nm and below, standby leakage current has dramatically increased and leakage power is becoming one of the most critical concerns for low power applications.This thesis analyzes some of the leakage current reduction techniques and proposes low power SRAM design based on data retention voltage (DRV) scheme. DRV defines the minimum standby voltage under which the SNM of a memory cell equals to zero and the data is still preserved. Reducing standby VDD to DRV not only greatly reduces leakage current but also preserves cell data.To avoid wasted leakage power saving for ensuring sufficient static noise margin, this thesis proposes a feedback monitor scheme to obtain approximate DRV tail of SRAM array. It utilizes the same memory cell with SRAM core cells and to get the corresponding supply voltage through data flipping features. Based on DRV dependencies on body-biasing and source-biasing voltage, we add controlling options to regulate the DRV of monitor cells and thus to obtain the tradeoff between power consumption and system reliability. The feedback monitor scheme for detecting DRV is applied to a 512Kb SRAM. The memory array is partitioned into small pieces by X, Y and Z decoding circuits. Combined with divided wordline/bitline techniques, dynamic power is significantly reduced. The voltage control circuit is implemented at the bank level, which puts most unused memory sections into low power mode to reduce the leakage current.Simulation results based on UMC 55nm CMOS process indicate that leakage power can be saved by 65.5% compared to conventional structure with little impact on performance penalty and data retention capability.