Study Of Digital IP Soft Core Design Method At RTL-level

Integrated circuit manufacturing process brings a new chip design times——SoC (System on Chip) stage.With the development of SoC, the entire system can be integrated on a chip.But this causes the chip design becoming increasingly complex. At the same time, some new design methods have also been generated. SoC design covers a very wide field, including embedded software, computer architecture, and the IP core design and multiplexing. SoC technology is a kind of IP core reuse design. In addition, IP core and the method of IP core design is critical. IP soft core which is not dependent on process distracts more and more attention. Therefore, how to design a portable digital circuit IP core has been becoming more and more important.Simple, reliable and efficient is the advantage of8bit microcontroller, which is why it is widely used in communications, industrial control and other fields. Recently, SCM has been greatly improved with instruction for structure and speed. RISC instruction set has also been applied to reduce the microcontroller's internal hardware instruction decoding time.8-bit microcontroller IP core is designed based on8-bit SCM. It can be used as a calculator and controller in a simple system;8bit CPU can still be used for module communication between the controller and data transfer in a complex SOC.This paper focuses on the digital IP soft core RTL-level design methodology. And then an8bit CPU IP soft-core design and application is used as an example for the research. Through this design, IP soft core RTL-level design methods and theories were verified and completed. CPU IP soft core functionality has been improved and complete validation in the project. Development and design of this project not only includes hardware design and verification, but also includes a software development designed to meet the characteristics of SoC development. The signal detection system has been successfully tested on FPGA and taped out with CSMC0.5um CMOS technology. The study of this paper presents relatively complete design and analysis method of mixing IP soft-core SoC design in RTL-level.