Research And Design Of Rf Modules Console Based On CPLD

RF Module Console is required for RF Module performance testing. The console and PC co-operation achieve precise control of RF module, so that the performance of the RF module can be measured by the external instruments, which can realize fault diagnosis and specific design testing of RF modules.Console design scheme is proposed based on the demand for work of RF module and console design specifications. This console achieves four functions:(1)providing a stable power supply for the RF module, (2) providing control signals for the RF module, (3) sending and receiving IF signal, (4) receiving the state signal of RF module.The console of the project builds a common data link channel platform based on Xilinx's CPLD XCR3384XL models, we adopt the enhanced parallel port EPP as a communication interfaces between PC and console. The data is entered to the console through software programming,then processed by console to achieve the control of the RF module.Console design includes board-level circuit design and CPLD system design. Board-level circuit implementation includes EPP parallel port expansion, the power circuit design, the IF signal transceiver end of the design and status signal receiver design. CPLD system includes EPP parallel port module, the data channel selection module, digital-control module, SPI modules. EPP parallel port module realize communication between PC and console, and realize the separation of address channel and data channel; Data channel selection module achieve control and choose of data channel and realize transmission of control signals; Digital-analog converter control module achieve precise control of Digital-analog converter; SPI function module realize the data cache, bit width conversion and string conversion and with the communication between multiple slaves. In the design of the SPI functional modules, the author extract the public parameters based on the timing requirements of RF module chipset, then determine the system clock speed is 10MHz, thus author can adopt a design method of module reuse with a purpose of reduce chip resources consumption. This paper designed a synchronous FIFO module to realize data cache and data conversion, compared with the traditional implementation, the module consumes fewer resources; slave machine selected module realize fast switching control for multiple slaves, while reducing waiting time between adjacent bytes.The simulation results of the designed module and the debug results of the console show that the proposed console can provides a power for RF module with voltage 7.2V, ripple less than 10mV, maximum current 3A, meanwhile, the proposed console can also transmit control signals properly, receive state signal and send and receive IF signal. Therefore, the design achieves the desired objectives.