Research Of Silicon CMOS MM-Wave Frequency Synthesizer Key Technologies

Nowadays, ultra-high-speed data transmission technology is developing rapidly.60GHz millimeter-wave communication systems have become a hot research topic for IC designers because it could accommodate the high throughput of multi-Gbps data transmission capacity. CMOS process is more and more highlighted and adopted for millimeter-wave communication system due to the advantages of low cost, high integration, etc. Frequency synthesizer, as one of the key modules of the60GHz communication system, is required to provide stable and high frequency signal with sufficient wide frequency range and low phase noise. In this paper, we design a CMOS frequency synthesizer to support transmission system of IEEE802.15.3c protocol.1. This article used the Cadence Virtuoso development Platform to design millimeter-wave CMOS integrated circuit. In the full-chip design, we use the transmission line PDK model as interconnect lines in MMIC. The application of transmission line has the advantages of improving the match between the chip modules, reducing the transmission loss between the chip modules, and enhancing the accuracy of post-simulation because of application of distributed parameter circuit model.2. This article optimized the inductor, the parasitic capacitance and resistance, and buffer amplifier for voltage controlled oscillator (VCO) especially in millimeter-wave band. Firstly, we analyzed the source of parasitic capacitor; amd applied a variety of parasitic capacitance optimization methods, including the structure of the NMOS cross-coupled VCO, the tree capacitor design; secondly, we designed physical model and ran simulation of the inductor and transmission line, analyzed the noise suppression mechanism, and use inductor and transmission line isolation techniques; thirdly, we used coupled coplanar waveguide as the VCO inductor, which could increase the quality factor of the resonant cavity, and further isolate substrate noise; Finally, we analyzed the optimal inductor in buffer amplifier design, and used a two-stage buffer hierarchy architecture.3. This article applied the proposed "NMOS/PMOS pair dual injection" injection locked frequency divider (ILFD) circuit structure to improve the ILFD injection locking range. Through post-simulation, the NMOS/PMOS pair dual injection has the best injection locking range which is1.5times of the injection locking range of traditional NMOS injection ILFD.4. We designed a frequency synthesizer which could meet requirements of protocol802.15.3c and802.11ad. The output frequency range is26.4GHz～33.5GHz, and the phase noise is103.6dBc/Hz at1MHz offset and115dBc/Hz at10MHz frequency offset. The PLL has power consumption of150mW. These indexes meet the requirements of PLL in design specifications802.15.3c transceiver in this paper.This work is supported in part by Shanghai Science and Technology Committee under Grant10706200202and Application Specific Integrated Circuit (ASIC) and Systems State Key Laboratory of Fudan University under Grant10KF013.